This invention relates, in general, to integrated circuit assembly and testing, and more particularly, to a batch process for assembly and test of integrated circuits.
A significant portion of the cost of integrated circuits (ICs) is incurred in packaging and testing. This is because packaging and testing are labor intensive operations which require repeated handling of individual packaged integrated circuits. Conventionally, good and bad ICs are mixed together during packaging. The packaged ICs are then burned-in and tested to remove the bad circuits. At this point, however, most of the cost of assembly and test has been incurred and so the rejected ICs are quite expensive.
Commonly, a batch of semiconductor devices are sorted into groups which have similar parameters. These groups or categories make up a particular device type, and are selected to meet a customer specification or an industry standard specification. Semiconductor memories in particular must be tested and sorted according to operating speed before shipping to a customer. In the past, this sorting was done after packaging, burn in, and parametric testing. While sorting does not usually produce a high number of rejects, performing sorting at this late step in the packaging/test process makes it difficult for a manufacturer to predict what particular device types will be available to sell. This lack of predictability makes production control difficult and results in product shipment delays to customers. Indeed, if no demand exists for a particular device type, packaged ICs which meet only the unwanted device type parameters must be scrapped or warehoused, which are both expensive options.
In addition to the cost incurred by packaging rejected and unwanted integrated circuits, additional cost is incurred because of damage induced by handling the individual packaged ICs. The mechanical operations involved in handling a packaged integrated circuit are complex. Damage to the package, or to leads which extend from the package, commonly occurs during burn-in, test, and package mark. The damage is usually caused by handling the individual packages, not by the operations themselves. Damage which occurs at these stages is usually not repairable and so good devices are scrapped.
In addition to the added yield loss, equipment used to handle packaged integrated circuits is usually expensive, and must be replicated for each operation. Thus, duplicate handling equipment must be provided for burn in, test, and mark. This equipment uses up a large amount of factory floor space, further increasing the overhead cost of assembly and test. Because handling equipment is mechanically complex, maintenance cost is usually high.
Accordingly it is an object of the present invention to provide an assembly and test flow for integrated circuits which significantly reduces the number of process steps.
A further object of the present invention is to provide an assembly and test flow for integrated circuits which allows manufacturers to evaluate parametric data before packaging the circuits.
It is another object of the present invention to provide an assembly and test flow for integrated circuits which improves cycle time.
It is another object of present invention to provide an assembly test flow which reduces equipment cost and floor space.
Another object of the present invention is to provide an assembly test flow for integrated circuits which improves quality.
Another object of the present invention is to provide an assembly test flow for integrated circuits which reduces the assembly and test costs added to those circuits.